Numerous steps are involved in the fabrication of microelectronic structures. Within the manufacturing scheme of fabricating integrated circuits, selective etching of semiconductor surfaces is sometimes required. Historically, a number of vastly different types of etching processes, to selectively remove material have been successfully utilized to varying degrees. Moreover, the selective etching of different layers, within the microelectronic structure, is considered a critical and crucial step in the integrated circuit fabrication process.
In the manufacture of semiconductors and semiconductor microcircuits, it is frequently necessary to coat substrate materials with a polymeric organic substance. Examples of some substrate materials includes titanium, copper, silicon dioxide coated silicon wafer which may further include metallic elements of titanium, copper, and the like. Typically, the polymeric organic substance is a photoresist material. This is a material which will form an etch mask upon development after exposure to light. In subsequent processing steps, at least a portion of the photoresist is removed from the surface of the substrate. One common method of removing photoresist from a substrate is by wet chemical means. The wet chemical compositions formulated to remove the photoresist from the substrate should do so without corroding, dissolving, and/or dulling the surface of any metallic circuitry; chemically altering the inorganic substrate; and/or attacking the substrate itself. Another method of removing photoresist is by a dry ash method where the photoresist is removed by plasma aching using either oxygen or forming gas such as hydrogen. The residues or by-products may be the photoresist itself or a combination of the photoresist, underlying substrate and/or etch gases. These residues or by-products are often referred to as sidewall polymers, veils or fences.
Increasingly, reactive ion etching (RIE) is the process of choice for pattern transfer during via, metal line and trench formation. For instance, complex semi-conductor devices such as advanced DRAMS and microprocessors, which require multiple layers of back end of line interconnect wiring, utilize RIE to produce vias, metal lines and trench structures. Vias are used, through the interlayer dielectric, to provide contact between one level of silicon, silicide or metal wiring and the next level of wiring. Metal lines are conductive structures used as device interconnects. Trench structures are used in the formation of metal line structures. Bottom antireflective coating (BARC) and gap fill materials, which are typically highly cross-linked organic polymer materials, are widely used in semiconductor substrates containing copper. BARC materials may also contain, for example, silicon. Vias, metal lines and trench structures typically expose metals and alloys such as Al—Cu, Cu, Ti, TiN, Ta, TaN, W, TiW, silicon or a silicide such as a silicide of tungsten, titanium or cobalt. The RIE process typically leaves a residue that may include re-sputtered oxide material as well as possibly organic materials from photoresist and antireflective coating materials used to lithographically define the vias, metal lines and or trench structures.
It would therefore be desirable to provide a selective cleaning composition and process capable of removing residues such as, for example, remaining photoresist, BARC and/or processing residues, such as for example, residues resulting from selective etching using plasmas and/or RIE. Moreover, it would be desirable to provide a selective cleaning composition and process, capable of removing residues such as photoresist, BARC and etching residue, that exhibits high selectivity for the residue as compared to metals, high dielectric constant materials (referred to herein as “high-k”), silicon, silicide and/or interlevel dielectric materials including low dielectric constant materials (referred to herein as “low-k”), such as deposited oxides that might also be exposed to the cleaning composition. It would be desirable to provide a composition that is compatible to and can be used with such sensitive low-k films as HSQ, MSQ, FOx, black diamond and TEOS (tetraethylsilicate).